TransportPi AES II, Flagship AES/SPDIF Transport

Introduction
TransportPi AES is a dedicated AES/EBU S/PDIF transport interface board. Compared with all other solutions, it is the first one that uses discrete 50Mbps 1-bit differential driver and dedicated femtosecond clock drivers to achieve the highest signal quality and lowest noise levels for both AES/EBU and S/PDIF outputs. And it also integrates the well-reputed multi-stages 1-bit discrete secondary re-clockers (similar to a ReClockPi) to ensure the best possible low-jitter performance. TransportPi AES is so far the flagship AES/EBU and S/PDIF transport interface board for audiophiles to improve the sound quality of an external DAC to a highest possible level.
TransportPi AES works in SYNC clock mode so it will need a FifoPiMa, FifoPiQ7 or Q3 to operate.

Highlighted Features and Specifications

• Flagship AES/EBU S/PDIF transport board with isolated AES/EBU, RCA, Toslink optical outputs and non-isolated BNC output
• Discrete 50Mbps 1-bit differential drive to achieve the best possible AES/EBU signal quality at the lowest noise levels
• Dedicated femtosecond clock drivers for S/PDIF outputs to achieve best possible signal quality and lowest jitter level
• Built-in the well-reputed 1-bit 3 stages discrete secondary re-clockers
  
• LDO free design to make it directly use the 3.3V ultracapacitor or battery power supply for the best power supply performance
• Could be so far the best AES/EBU and S/PDIF streamer transport interface
• Optimized PCB impedance control for the high speed AES/EBU and S/PDIF signals
• 4 layers PCB design with dedicate shield layers to eliminate EMI noise
• Metal film ultra-low noise resistors to ensure the lowest possible noise level
• Pure sync mode works with FifoPiQ7, FifoPiMa or FifoPiQ3 or other re-clockers.
• Capable of AES/EBU and S/PDIF up to 192KHz. 384KHz is also possible for qualified receiver
• Upgradable and swapable AES/EBU, S/PDIF transformers
• Supports MCLK frequencies from 5.6448MHz to 98.304MHz
• Supports I2S and DoP format as input

TransportPi AES II (2026) New Features

• Featuring new 7.5 fs ultra-low additive jitter clock drivers for both MCLK and S/PDIF signals. This advanced clocking architecture dramatically reduces phase noise to ensure the highest level of sonic purity
• Higher quality, more durable SPDIF/AES digital transformers
• Enhanced power supply filtering/conditioning networks featuring ultra-low ESR and high bandwidth to achieve lowest possible power supply noise floor
• Precision manufacturing to ensure top level hardware engineering quality
• A slightly larger PCB size with improved silkscreen markings for enhanced legibility

TransportPi AES II User's Manual

(Old) TransportPi AES User's manual

TransportPi Comparison

Project Examples