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#9. I2S to PCM converter board V2.0

#9. I2S to PCM converter board V2.0

Regular price $79.00
Regular price Sale price $79.00
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Many people still like the sound of traditional MULTIBIT audio DACs, such as AD1865/62, PCM1704/02, PCM63, TDA1541/A, and many others, because they convert digital music into analog in a different way than popular DELTA-SIGMA DACs.
However, most of those MULTIBIT DACs were designed having to work with digital filter chip through an interface we called "PCM", which transmits left and right data simultaneously. In this case, the problem would be that the sound quality and the maximum Fs of MULTIBIT DACs can be limited by the performance of the hardware based over sampling digital filter chip due to the low internal calculating accuracy, the resource saving interpolating algorithm, and the old higher jitter hardware technology.
In order to boost the sound quality by introducing low jitter technology and to play higher Fs music, we need to get rid of the limitation of that digital filter chip by driving the MULTIBIT DAC from higher performance software base real-time up-sampling filter or high Fs music stream directly. So, we need a jitter optimized device to run MULTIBIT DAC at NOS mode from an I2S bus.
This I2S to PCM converter board was developed exactly for this purpose under the requirement of audiophiles.


  1. Support 16,18,20,24 bit PCM format output
  2. Accept 16 to 32bit I2S input signals with SCK from 32*Fs to 64*Fs
  3. Pure NOS mode with bit-perfect format converting
  4. High speed design capable for 384KHz Fs with maximum MCLK up to 100MHz
  5. Support PCM63,AD1865,AD1862,PCM1704,PCM1702,TDA1541/A and many other classical MULTIBIT DACs
  6. Support TDA1541/A working at offset binary mode
  7. Jumper selectable full-speed mode and half-speed mode
  8. L,R simultaneous timing, launching D/A conversion at same latching edge to eliminate L/R phase difference
  9. In order to reduce DAC noise floor, bit clock can be stopped after data shifted into DAC (default)
  10. Delayed falling edge of latch enable signal (LLLR) applied to stop clock mode
  11. Support dual mono DAC configuration
  12. Jitter optimized synchronize logic architecture with last stage high speed low noise re-clocking flip-flops driven by original MCLK
  13. With same physical dimensions, it can be assembled stacking on top of the FIFO clock board to save space

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